LVMVIP

Features

Unlimited instances.
Supports sending all types of AHB stimulus for AHB4 and AHB5.
Supports cancel packet scenario while bad HRESP, idle, busy etc injection into AHB traffic.
Support AHB master and slaves
Ease of control for sending AHB in any timing sequences (as AHB master), in pipelined or waited mode.
Provides complete configuration parameters to control AHB VIP.
RAL-ready where adaptor and predictor are built-in and ready to pair with user’s regmodel.
Provide API for register partial access verification (byte and hword accesses), in compliment for bit-bashing verification by UVM.
API-based reset-aware UVM Component which is user friendly for non UVM experienced engineers and designers.
Comes with complete Compliance and Regression testsuite to verify AHB slave memory, protocol checks, out of bound memory access etc
Integrated ARM AHB SVA embedded for protocol compliance check with assertion coverage.
On-the-fly protocol and data integrity checking.
Useful signals and events at waveforms for high debug-ability like packet counter, output sampling, signal enums etc
Comprehensive tracker log for AHB bus activities including byte address activity tracker.
End of test memory printing and bus activity statistic summary.
Fully parameterizable signal widths.
Includes Reference Verification testbench for easy integration, configuration and setup.
Includes sample scoreboard to fetch sequence item from the UVC.
Setup and hold verification by clocking block mechanism and X injection.