JTAG

Features

Unlimited instances.
Supports sending all types of JTAG stimulus.
Support JTAG master and slave.
Ease of control for sending JTAG in any timing sequences (as JTAG master).
Provides complete configuration parameters to control JTAG VIP.
API-based reset-aware UVM Component which is user friendly for non UVM experienced engineers and designers.
Useful signals and events at waveforms for high debug-ability like serial data value, data sampling timing, TAP state etc
End of test memory printing and bus activity statistic summary.
Fully parameterizable instruction width, scan width, and user define register width etc.
Includes Reference Verification testbench for easy integration, configuration and setup.
Includes sample scoreboard to fetch sequence item from the UVC.