• 1 license is all you need!
• We don’t mind how many instances you have in the testbench, how many parallel simulation with our VIP in action!

• Support AXI master and slaves
• Fully parameterizable signal widths
• Support out of order B or R, and they are configurable

• To smoothen and speed up user on integrating, configuring, and setting up the VIP, we specially      prepared a reference Verification testbench.
• API-based, reset-aware UVM Component which is user friendly for non UVM experienced engineers and designers, yes, non UVM engineers can use our VIP easily also!
• Includes sample scoreboard to fetch sequence item / transaction from the UVC.
• RAL-ready where adaptor and predictor are built-in and ready to pair with user’s regmodel.

• Supports sending all types of AXI stimulus for AXI3, AXI4, AXI4-Lite, including low power features.
• Ease of control for sending AXI in AW, W, AR channels in any timing sequences (as AXI master), including injecting delays or in concurrent sending.
• Provide API for register partial access verification (byte and hword accesses), in compliment for bit-bashing verification by UVM.
• Setup and hold verification by clocking block mechanism and X injection.

• We provide complete Compliance and Regression testsuite with total 80++ test scenarios for SOC verification
• Verification Targets:
  1. AXI slave memory controllers
  2. AXI fabric / Interconnect in your SOC
     1. Outstanding transaction threshold
     2. AXI protocol checks, 
     3. Out of bound memory access

• Datapath from CPU to memories will be fully tested with full blast of AXI random packets, regardless of memory characteristic 

               1.  ROM (read only), SRAM

               2. Support limited AxSIZE or bus width size

• We are the first in the industry that able to do the above (and most probably you can never find any other VIP that can), with just 1 line API! 
  1. Launch burst write to target registers, and burst read to check the register, supporting all kind of access of the registers (RW, RO, WO, W1C etc)
  2. Target the register read write with size lesser than the bus size
  3. Confirm in your DUT does not have address aliasing problem (for example, programming address 104h, will touch the register at 04h)
  4. Confirm the unused address of registers are RO and returning 0 (configurable)

• It is not just AXI VIP, it has the advanced bit bashing API.
• Register verification has been further simplified!
• Advanced control of register verification flow / sequence of order.
• Auto cover scenario below:

               1. Register A controls Register B access (like lock and unlock case)

               2. Set / Clear/ Toggle register verification

• Useful signals and events at waveforms for high debug-ability like packet      counter, effective address, effective data, corresponding ID etc
• Comprehensive tracker log for AXI bus activities including byte address activity tracker.
  1. Ease of debug when tracing read write activity toward address with data mismatch.
  2. Educational where it helps new AXI user understands AXI protocol and data placement in byte lanes etc.

• Integrated ARM AXI SVA embedded for protocol compliance check with assertion      coverage.
• On-the-fly protocol and data integrity, and response checking.
• Timeout mechanism for waiting ready signal

• Performance checking for wait latency.
• End of test memory printing and bus activity statistic summary.

• Our self verification testbench not only demonstrate the VIP usage / configuring the VIP, but also educational. User can learn:
  1. The concept of uvm testbench architecture
  2. Makefile techniques
  3. RAL frontdoor and backdoor access
  4. Wire assignment techniques for input / output signals