Supports sending all types of AXI stimulus for AXI3, AXI4, AXI4-Lite, including low power features.
Support AXI master and slaves
Ease of control for sending AXI in AW, W, AR channels in any timing sequences (as AXI master), including injecting delays or in concurrent sending.
Provides complete configuration parameters to control AXI VIP.
Timeout mechanism while waiting ready signal
RAL-ready where adaptor and predictor are built-in and ready to pair with user’s regmodel.
Provide API for register partial access verification (byte and hword accesses), in compliment for bit-bashing verification by UVM.
API-based reset-aware UVM Component which is user friendly for non UVM experienced engineers and designers.
Comes with complete Compliance and Regression testsuite to verify AXI slave memory, outstanding transaction threshold, protocol checks, out of bound memory access etc
Integrated ARM AXI SVA embedded for protocol compliance check with assertion coverage.
On-the-fly protocol and data integrity checking.
Performance checking for wait latency.
Useful signals and events at waveforms for high debug-ability like packet counter, effective address, effective data, corresponding ID etc
Comprehensive tracker log for AXI bus activities including byte address activity tracker.
End of test memory printing and bus activity statistic summary.
Fully parameterizable signal widths.
Includes Reference Verification testbench for easy integration, configuration and setup.
Includes sample scoreboard to fetch sequence item from the UVC.
Setup and hold verification by clocking block mechanism and X injection.
We use cookies to analyze website traffic and optimize your website experience. By accepting our use of cookies, your data will be aggregated with all other user data.